1. Field of the Invention
The present invention relates in general to a process for semiconductor memory device fabrication. In particular, the present invention relates to a process for the fabrication of high-density read-only memory devices utilizing a liquid-phase deposition-coding oxide layer to improve process alignment and eliminate variations in device characteristics. More particularly, the present invention relates to a process for the fabrication of high-density read-only memory devices with improved process alignment and elimination of variations in device characteristics while providing for the storage of more than one bit of binary data within a single memory cell.
2. Technical Background
Semiconductor read-only memory (ROM) devices, in particular, masked ROM's, are enjoying the advantages brought about by miniaturization resulting from the continuing advancements in semiconductor technology. Among the most apparent advantages is an increase in memory storage capacity. More and more memory cells can be packed into the same semiconductor die area during commercial mass production of the ROM devices. Along with the process of device miniaturization, the architectural configuration of the mask ROM memory cell has undergone a series of changes, from the traditional two-state memory cell configurations to the x-cell, the flat cell, and, lately, the modified flat cell. These cell configuration improvements have propelled commercial mask ROM devices from the 128K, through 256K, and up to the 16M, even 32M-bit storage capacity levels. These ever increasing capacity mask ROM devices are being manufactured into integrated circuits having reasonable commercially feasible chip sizes.
Coding, that is, the programming of the memory contents of conventional mask ROM devices, is typically implemented by implanting impurities into the channel regions of the selected memory cell transistors of the mask ROM device. The goal is to set the threshold voltage in the channel regions of the memory cell transistors, so that the transistors may be "coded" or "programmed" into their conducting or blocking states, which may be interpreted by auxiliary circuitry of the mask ROM device to be either binary "0" or "1" data bits.
However, the technique of ion implantation to accomplish the mask ROM memory cell content coding reveals some phenomena that are disadvantageous for the miniaturization of mask ROM devices. In particular, the lateral diffusion phenomena of the implanted impurities, as well as the increased difficulties of alignment as the devices get smaller and the fabrication resolution gets finer, makes it more difficult to control the characteristics of the mask ROM devices fabricated.
Further, the use of single memory cells in the memory array of the ROM devices to store one bit of data is a limitation of current semiconductor storage systems. The use of a single memory cell for the storage of more than one bit of data, or the equivalent of more than one bit of binary data, will provide for the expansion of ROM device storage capacity within a semiconductor device of the same physical size.
A brief examination of the semiconductor structural configuration of the memory cell of a prior art mask ROM device will help to lay the foundation for the description of the present invention. FIGS. 1-3 of the accompanying drawing of the present invention depict the characteristics of the memory cell of a conventional mask ROM device when the coding thereof is concerned, wherein FIG. 1 is the top view, and FIGS. 2 and 3 are the cross-sectional views of the memory cell respectively as selected from the designated cross-sectional lines in FIG. 1.
As can be seen in the drawing, the memory cell of the conventional mask ROM device is fabricated over semiconductor silicon substrate 10 having been doped therein with P-type impurities. Source/drain regions 11 are formed by the implantation of N-type impurities into the designated regions on the substrate that extend along a designated direction in substrate 10 to form the bit lines for the memory array of the mask ROM device. Gate oxide layer 12 is then formed to cover substrate 10, with the formation of gate electrodes 13 that extend along a second direction over the surface of substrate 10. In general, the longitudinal directions of gate electrodes 13 will be orthogonal to the longitudinal directions of source/drain regions 11. Gate electrodes 13 also constitute the word lines for the memory array of the mask ROM device.
Every region of substrate 10, namely, the region confined between every two adjacent bit lines that is beneath the word line, constitutes the channel region for a memory cell transistor for the mask ROM memory array. The memory cell transistor will be made, or, coded either into its state of conduction or blocking, depending on the specific requirement that the cell should be storing either a binary 1or 0 data bit. The correspondence of the status of channel region conductance and the bit value of stored data bit is dependent on the design of the device, as mentioned above. However, the key to the coding of the transistor for a particular cell to be in its blocking state, is to implant P-type impurities into the channel region of the selected memory cell transistor.
The presence of the implanted impurities via the code implant procedure allows the raising of the threshold voltage of that memory cell transistor channel region. This code implant procedure, in the case of the conventional mask ROM devices, may be done by applying photoresist layer 14 covering the surface of substrate 10, but with exposed coding openings 15 that allows for the ion implantation procedure to implant the required impurities with the designated concentration into the exposed channel regions of the selected memory cell transistors.
The coding procedure, namely, the ion implantation procedure, requires that the impurities be precisely implanted into the designated channel regions of the memory cell transistors as selected by coding openings 15 that are formed in photoresist layer 14. This means that the alignment of photoresist layer 14 over substrate 10 must be sufficiently precise, so that a coding opening reveals the channel region that is supposed to be between two consecutive bit lines and beneath one word line. As persons skilled in the art may well aware, as the size of the memory cells get ever smaller, and the fabrication resolution becomes finer, this task of precision alignment has becomes more and more difficult. On the other hand, the inherent phenomena of impurity lateral diffusion also requires that safety space be reserved for the periphery of the channel region, so that the most important characteristics of memory cell transistor conductance can be precisely controlled. These factors, however, create difficulties for device miniaturization.